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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_fg_05_21.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity full_adder is
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  port ( a, b, c_in : bit;  s, c_out : out bit );
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end entity full_adder;
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architecture truth_table of full_adder is
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begin
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  with bit_vector'(a, b, c_in) select
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    (c_out, s) <= bit_vector'("00") when "000",
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    bit_vector'("01") when "001",
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    bit_vector'("01") when "010",
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    bit_vector'("10") when "011",
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    bit_vector'("01") when "100",
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    bit_vector'("10") when "101",
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    bit_vector'("10") when "110",
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    bit_vector'("11") when "111";
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end architecture truth_table;
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-- not in book
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entity fg_05_21 is
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end entity fg_05_21;
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library stimulus;
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use stimulus.stimulus_generators.all;
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architecture test of fg_05_21 is
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  signal a, b, c_in, s, c_out : bit;
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  signal test_vector : bit_vector(1 to 3);
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begin
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  dut : entity work.full_adder
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    port map ( a => a, b => b, c_in => c_in, s => s, c_out => c_out );
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  all_possible_values ( test_vector, 10 ns );
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  (a, b, c_in) <= test_vector;
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end architecture test;
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-- end not in book
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