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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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5
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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10
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_ch_05_24.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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-- code from book:
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28
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entity and3 is
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port ( a, b, c : in bit := '1';
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z, not_z : out bit);
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end entity and3;
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33
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-- end of code from book
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35
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36
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architecture functional of and3 is
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begin
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non_inverting:
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z <= a and b and c;
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41
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inverting:
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not_z <= not (a and b and c);
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44
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end architecture functional;
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46
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entity ch_05_24 is
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48
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end entity ch_05_24;
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50
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library stimulus;
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52
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architecture test of ch_05_24 is
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54
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signal s1, s2, ctrl1_a, ctrl1_b : bit;
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signal test_input : bit_vector(1 to 2);
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57
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use stimulus.stimulus_generators.all;
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59
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begin
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block_05_4_a : block is
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port ( ctrl1 : out bit );
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port map ( ctrl1 => ctrl1_a );
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begin
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-- code from book:
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69
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g1 : entity work.and3 port map (a => s1, b => s2, not_z => ctrl1);
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71
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-- end of code from book
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73
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end block block_05_4_a;
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75
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block_05_4_b : block is
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port ( ctrl1 : out bit );
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port map ( ctrl1 => ctrl1_b );
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begin
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-- code from book:
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82
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g1 : entity work.and3 port map (a => s1, b => s2, not_z => ctrl1,
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c => open, z => open);
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85
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-- end of code from book
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87
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end block block_05_4_b;
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89
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stimulus_proc : all_possible_values( bv => test_input,
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delay_between_values => 10 ns );
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92
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(s1, s2) <= test_input;
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94
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verifier :
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assert ctrl1_a = ctrl1_b
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report "versions differ";
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98
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end architecture test;
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