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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_ch_05_21.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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-- code from book:
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entity and_gate is
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  port ( i : in bit_vector;  y : out bit );
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end entity and_gate;
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-- end of code from book
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architecture behavioral of and_gate is
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begin
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  reducer : process (i) is
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                          constant Tpd : delay_length := 2 ns;
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                        variable result : bit;
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  begin
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    result := '1';
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    for index in i'range loop
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      result := result and i(index);
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    end loop;
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    y <= result after Tpd;
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  end process reducer;
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end architecture behavioral;
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entity ch_05_21 is
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end entity ch_05_21;
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library stimulus;
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architecture test of ch_05_21 is
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  -- code from book:
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  signal serial_select, write_en, bus_clk, serial_wr : bit;
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  -- end of code from book
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  use stimulus.stimulus_generators.all;
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  signal test_input : bit_vector(2 downto 0);
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begin
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  -- code from book:
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  serial_write_gate : entity work.and_gate
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    port map ( i(1) => serial_select,
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               i(2) => write_en,
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               i(3) => bus_clk,
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               y => serial_wr );
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  -- end of code from book
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  stimulus_proc : all_possible_values( bv => test_input,
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                                  delay_between_values => 10 ns );
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  (serial_select, write_en, bus_clk) <= test_input;
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end architecture test;
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