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ERROR: Unable to parse source file : /home/adieumeg/Documents/Repositories/lustrec-tests/vhdl_json/vhdl_files/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_18.vhd
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ERROR: Parse error at line 63 column 18:
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53: ----------------------------------------------------------------
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56: architecture test of ch_05_18 is
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60: begin
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63:   block_05_4_a : block is
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                     ^
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64:                          signal cpu_rd, cpu_wr, cpu_mem,
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65:                        mem_ras, mem_cas, mem_we, cpu_rdy : bit;
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66:   begin
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67: 
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68:     -- code from book:
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69: 
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70:     main_mem_controller : entity work.DRAM_controller(fpld)
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71:       port map ( cpu_rd, cpu_wr, cpu_mem,
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72:                  mem_ras, mem_cas, mem_we, cpu_rdy );
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73: 
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WARN: Missing blame information for the following files:
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WARN:   * ch_05_ch_05_18.vhd
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WARN: This may lead to missing/broken features in SonarQube
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