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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_ch_05_15.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_05_15 is
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  generic ( extended_reset : boolean := false );
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end entity ch_05_15;
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----------------------------------------------------------------
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architecture test of ch_05_15 is
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  signal functional_reset, equivalent_reset : bit := '0';
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begin
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  block_05_3_r : block is
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                         port ( reset : out bit );
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                       port map ( reset => functional_reset );
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  begin
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    -- code from book:
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    reset_gen : reset <= '1', '0' after 200 ns when extended_reset else
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                         '1', '0' after 50 ns;
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    -- end of code from book
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  end block block_05_3_r;
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  ----------------
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  block_05_3_s : block is
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                         port ( reset : out bit );
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                       port map ( reset => equivalent_reset );
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  begin
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    -- code from book:
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    reset_gen : process is
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    begin
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      if extended_reset then
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        reset <= '1', '0' after 200 ns;
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      else
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        reset <= '1', '0' after 50 ns;
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      end if;
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      wait;
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    end process reset_gen;
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    -- end of code from book
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  end block block_05_3_s;
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  ----------------
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  verifier :
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    assert functional_reset = equivalent_reset
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      report "Functional and equivalent models give different results";
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end architecture test;
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