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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_ch_05_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_05_07 is
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end entity ch_05_07;
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----------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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architecture test of ch_05_07 is
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  signal clk, d : std_ulogic;
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  constant Tpw_clk : delay_length := 10 ns;
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  constant Tsu : delay_length := 4 ns;
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begin
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  process_05_3_c : process (clk, d) is
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  begin
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    -- code from book:
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    if clk'event and (clk = '1' or clk = 'H')
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      and (clk'last_value = '0' or clk'last_value = 'L') 
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    then
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      assert d'last_event >= Tsu
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        report "Timing error: d changed within setup time of clk";
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    end if;
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    -- end of code from book
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  end process process_05_3_c;
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  ----------------
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  process_05_3_d : process (clk, d) is
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  begin
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    -- code from book:
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    assert (not clk'event) or clk'delayed'last_event >= Tpw_clk
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      report "Clock frequency too high";
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    -- end of code from book
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  end process process_05_3_d;
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  ----------------
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  process_05_3_e : process is
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  begin
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    -- code from book:
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    wait until clk = '1';
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    -- end of code from book
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    report "clk changed to '1'";
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  end process process_05_3_e;
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  ----------------
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  stimulus_05_3_c_d : process is
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  begin
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    clk <= '1' after  15 ns,
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           '0' after  30 ns,
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           '1' after  40 ns,
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           '0' after  50 ns,
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           'H' after  60 ns,
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           '0' after  70 ns,
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           '1' after  80 ns,
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           'L' after  90 ns,
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           'H' after 100 ns,
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           'L' after 120 ns,
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           '1' after 125 ns, -- should cause error
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           '0' after 130 ns; -- should cause error
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    d <= '1' after  35 ns,
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         '0' after  77 ns, -- should cause error
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         '1' after 102 ns;
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    wait;
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  end process stimulus_05_3_c_d;
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end architecture test;
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