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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_04_fg_04_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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architecture system_level of computer is
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type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, -- . . .);
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-- not in book:
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nop);
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-- end not in book
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type reg_number is range 0 to 31;
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constant r0 : reg_number := 0; constant r1 : reg_number := 1; -- . . .
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-- not in book:
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constant r2 : reg_number := 2;
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-- end not in book
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type instruction is record
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opcode : opcodes;
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source_reg1, source_reg2, dest_reg : reg_number;
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displacement : integer;
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end record instruction;
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type word is record
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instr : instruction;
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data : bit_vector(31 downto 0);
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end record word;
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signal address : natural;
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signal read_word, write_word : word;
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signal mem_read, mem_write : bit := '0';
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signal mem_ready : bit := '0';
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begin
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cpu : process is
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variable instr_reg : instruction;
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variable PC : natural;
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-- . . . -- other declarations for register file, etc.
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begin
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address <= PC;
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mem_read <= '1';
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wait until mem_ready = '1';
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instr_reg := read_word.instr;
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mem_read <= '0';
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-- not in book:
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wait until mem_ready = '0';
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-- end not in book
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PC := PC + 4;
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case instr_reg.opcode is -- execute the instruction
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-- . . .
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-- not in book:
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when others => null;
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-- end not in book
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end case;
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end process cpu;
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memory : process is
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type memory_array is array (0 to 2**14 - 1) of word;
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variable store : memory_array :=
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( 0 => ( ( ld, r0, r0, r2, 40 ), X"00000000" ),
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1 => ( ( breq, r2, r0, r0, 5 ), X"00000000" ),
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-- . . .
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40 => ( ( nop, r0, r0, r0, 0 ), X"FFFFFFFE"),
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others => ( ( nop, r0, r0, r0, 0 ), X"00000000") );
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begin
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-- . . .
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-- not in book:
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wait until mem_read = '1';
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read_word <= store(address);
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mem_ready <= '1';
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wait until mem_read = '0';
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mem_ready <= '0';
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-- end not in book
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end process memory;
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end architecture system_level;
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