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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_04_ch_04_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_04_02 is
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end entity ch_04_02;
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----------------------------------------------------------------
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architecture test of ch_04_02 is
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begin
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  process_04_1_b : process is
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                             -- code from book:
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                             type symbol is ('a', 't', 'd', 'h', digit, cr, error);
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                           type state is range 0 to 6;
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                           type transition_matrix is array (state, symbol) of state;
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                           variable transition_table : transition_matrix;
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                           -- end of code from book
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                           variable next_state : state;
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                           -- code from book:
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                           type point is array (1 to 3) of real;
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                           type matrix is array (1 to 3, 1 to 3) of real;
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                           variable p, q : point;
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                           variable transform : matrix;
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                           -- end of code from book
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  begin
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    next_state := 
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      -- code from book:
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      transition_table(5, 'd');
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    -- end of code from book
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    for i in 1 to 3 loop
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      for j in 1 to 3 loop
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        if i = j then
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          transform(i, j) := -1.0;
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        else
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          transform(i, j) := 0.0;
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        end if;
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      end loop;
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    end loop;
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    p := (1.0, 2.0, 3.0);
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    -- code from book:
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    for i in 1 to 3 loop
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      q(i) := 0.0;
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      for j in 1 to 3 loop
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        q(i) := q(i) + transform(i, j) * p(j);
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      end loop;
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    end loop;
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    -- end of code from book
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    wait;
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  end process process_04_1_b;
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end architecture test;
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