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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_04_ch_04_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_04_01 is
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end entity ch_04_01;
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----------------------------------------------------------------
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architecture test of ch_04_01 is
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begin
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  block_04_1_a : block is
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                         -- code from book:
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                         type word is array (0 to 31) of bit;
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                       --
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                       type controller_state is (initial, idle, active, error);
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                       type state_counts is array (idle to error) of natural;
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                       -- end of code from book
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  begin
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  end block block_04_1_a;
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  process_04_1_a : process is
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                             -- code from book:
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                             type word is array (31 downto 0) of bit;
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                           --
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                           type controller_state is (initial, idle, active, error);
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                           --
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                           type state_counts is
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                             array (controller_state range idle to error) of natural;
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                           --
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                           subtype coeff_ram_address is integer range 0 to 63;
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                           type coeff_array is array (coeff_ram_address) of real;
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                           --
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                           variable buffer_register, data_register : word;
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                           variable counters : state_counts;
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                           variable coeff : coeff_array;
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                           -- end of code from book
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  begin
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    -- code from book:
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    coeff(0) := 0.0;
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    counters(active) := counters(active) + 1;
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    data_register := buffer_register;
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    -- end of code from book
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    wait;
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  end process process_04_1_a;
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end architecture test;
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