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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_03_tb_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity test_bench_03_03 is
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end entity test_bench_03_03;
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library ieee;  
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use ieee.std_logic_1164.all;
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architecture test_mux4_demo of test_bench_03_03 is
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  signal sel : work.test_bench_03_02.sel_range := 0;
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  signal d0, d1, d2, d3, z : std_ulogic;
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begin
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  dut : entity work.mux4(demo)
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    port map ( sel => sel,
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               d0 => d0, d1 => d1, d2 => d2, d3 => d3,
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               z => z );
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  stimulus : process is
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  begin
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    wait for 5 ns;
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    d0 <= '1';			wait for 5 ns;
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    d1 <= 'H';			wait for 5 ns;
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    sel <= 1;	wait for 5 ns;
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    d1 <= 'L';			wait for 5 ns;
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    sel <= 2;	wait for 5 ns;
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    d0 <= '0';			wait for 5 ns;
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    d2 <= '1';			wait for 5 ns;
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    d2 <= '0';			wait for 5 ns;
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    sel <= 3;	wait for 5 ns;
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    d3 <= '1';			wait for 5 ns;
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    d3 <= '0';			wait for 5 ns;
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    wait;
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  end process stimulus;
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end architecture test_mux4_demo;
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