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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_03_ch_03_12.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity ch_03_12 is
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end entity ch_03_12;
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architecture test of ch_03_12 is
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begin
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process_3_4_a : process is
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constant condition, condition_1,
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condition_2, condition_3 : boolean := true;
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variable index : integer;
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begin
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-- code from book: syntax check only
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-- change "condition" to roman italic
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-- not in book:
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loop
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-- end not in book
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if condition then
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exit;
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end if;
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-- not in book:
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end loop;
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-- end not in book
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--
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-- change "condition" to roman italic
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loop
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-- . . .
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exit when condition;
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-- . . .
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end loop;
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-- . . . -- control transferred to here
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-- when condition becomes true within the loop
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--
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loop_name : loop
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-- . . .
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exit loop_name;
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-- . . .
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end loop loop_name ;
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--
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-- change conditions to roman italic with hyphens
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outer : loop
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-- . . .
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inner : loop
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-- . . .
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exit outer when condition_1; -- exit 1
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-- . . .
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exit when condition_2; -- exit 2
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-- . . .
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end loop inner;
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-- . . . -- target A
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exit outer when condition_3; -- exit 3
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-- . . .
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end loop outer;
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-- . . . -- target B
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--
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-- "statement..." in roman italic with hyphens
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loop
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-- statement_1;
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next when condition;
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-- statement_2;
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end loop;
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--
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-- "statement..." in roman italic with hyphens
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loop
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-- statement_1;
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if not condition then
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-- statement_2;
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end if;
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end loop;
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--
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while index > 0 loop
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-- . . . -- statement A: do something with index
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end loop;
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-- . . . -- statement B
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-- end of code from book
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wait;
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end process process_3_4_a;
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end architecture test;
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