|
1
|
|
|
2
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
|
|
3
|
|
|
4
|
-- This file is part of VESTs (Vhdl tESTs).
|
|
5
|
|
|
6
|
-- VESTs is free software; you can redistribute it and/or modify it
|
|
7
|
-- under the terms of the GNU General Public License as published by the
|
|
8
|
-- Free Software Foundation; either version 2 of the License, or (at
|
|
9
|
-- your option) any later version.
|
|
10
|
|
|
11
|
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
|
|
12
|
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
13
|
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
|
14
|
-- for more details.
|
|
15
|
|
|
16
|
-- You should have received a copy of the GNU General Public License
|
|
17
|
-- along with VESTs; if not, write to the Free Software Foundation,
|
|
18
|
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
19
|
|
|
20
|
-- ---------------------------------------------------------------------
|
|
21
|
--
|
|
22
|
-- $Id: ch_01_tb_01_01.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
|
|
23
|
-- $Revision: 1.2 $
|
|
24
|
--
|
|
25
|
-- ---------------------------------------------------------------------
|
|
26
|
|
|
27
|
entity test_bench_01_01 is
|
|
28
|
|
|
29
|
end entity test_bench_01_01;
|
|
30
|
|
|
31
|
architecture test_reg4_behav of test_bench_01_01 is
|
|
32
|
|
|
33
|
signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
|
|
34
|
|
|
35
|
begin
|
|
36
|
|
|
37
|
dut : entity work.reg4(behav)
|
|
38
|
port map ( d0 => d0, d1 => d1, d2 => d2, d3 => d3, en => en, clk => clk,
|
|
39
|
q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
|
|
40
|
|
|
41
|
stimulus : process is
|
|
42
|
begin
|
|
43
|
wait for 20 ns;
|
|
44
|
(d0, d1, d2, d3) <= bit_vector'("1010"); wait for 20 ns;
|
|
45
|
en <= '1'; wait for 20 ns;
|
|
46
|
clk <= '1'; wait for 20 ns;
|
|
47
|
(d0, d1, d2, d3) <= bit_vector'("0101"); wait for 20 ns;
|
|
48
|
clk <= '0'; wait for 20 ns;
|
|
49
|
(d0, d1, d2, d3) <= bit_vector'("0000"); wait for 20 ns;
|
|
50
|
en <= '1'; wait for 20 ns;
|
|
51
|
(d0, d1, d2, d3) <= bit_vector'("1111"); wait for 20 ns;
|
|
52
|
|
|
53
|
wait;
|
|
54
|
end process stimulus;
|
|
55
|
|
|
56
|
end architecture test_reg4_behav;
|