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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ap_a_fg_a_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity fg_a_01 is
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end entity fg_a_01;
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library ieee;  use ieee.std_logic_1164.all;
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architecture test of fg_a_01 is
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  signal clk, d : std_ulogic;
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begin
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  stimulus : process is
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  begin
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    clk <= '0';  d <= '0';  wait for 10 ns;
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    clk <= '1', '0' after 10 ns;  wait for 20 ns;
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    d <= '1';  wait for 10 ns;
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    clk <= '1', '0' after 20 ns;  d <= '0' after 10 ns;
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    wait;
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  end process stimulus;
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  b1 : block is
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               signal q : std_ulogic;
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  begin
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    -- code from book
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    process (clk) is
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    begin
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      if rising_edge(clk) then
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        q <= d;
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      end if;
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    end process;
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    -- end code from book
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  end block b1;
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  b2 : block is
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               signal q : std_ulogic;
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  begin
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    -- code from book
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    process is
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    begin
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      wait until rising_edge(clk);
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      q <= d;
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    end process;
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    -- end code from book
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  end block b2;
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  b3 : block is
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               signal q : std_ulogic;
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  begin
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    -- code from book
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    q <= d when rising_edge(clk) else
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         q;
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    -- end code from book
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  end block b3;
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  b4 : block is
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               signal q : std_ulogic;
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  begin
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    -- code from book
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    b : block ( rising_edge(clk)
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                and not clk'stable ) is
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    begin
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      q <= guarded d;
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    end block b;
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    -- end code from book
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  end block b4;
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end architecture test;
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