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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ap_a_ap_a_03.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ap_a_03 is
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end entity ap_a_03;
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library ieee;  use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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architecture test of ap_a_03 is
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begin
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  b1 : block is
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               -- code from book
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               type unsigned is array ( natural range <> ) of std_logic;
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             type signed is array ( natural range <> ) of std_logic;
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             -- end code from book
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  begin
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  end block b1;
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  b2 : block is
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               -- code from book
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               signal a: integer := 0;
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             signal b: signed (4 downto 0 );
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             -- end code from book
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  begin
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    a <= 0, 5 after 10 ns, -5 after 20 ns, 8 after 30 ns;
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    -- code from book
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    b <= To_signed ( a, b'length );
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    -- end code from book
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    process (b) is
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    begin
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      -- code from book
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      if std_match ( b, "0-000" ) then
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        -- . . .
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        -- end code from book
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        report "b matches";
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      else
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        report "b does not match";
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      end if;    
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    end process;
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  end block b2;
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end architecture test;
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