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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_15_mem-pl.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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library bv_utilities;
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use bv_utilities.bv_arithmetic.all;
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architecture preloaded of memory is
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begin
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mem_behavior : process is
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constant high_address : natural := mem_size - 1;
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type memory_array is
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array (natural range 0 to high_address / 4) of dlx_bv_word;
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variable mem : memory_array
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:= ( X"20020000", -- addi r2, r0, 0
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X"ac020018", -- loop: sw counter(r0), r2
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X"20420001", -- addi r2, r2, 1
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X"6441000a", -- snei r1, r2, 10
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X"1420fff0", -- bnez r1, loop
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X"44000000", -- trap 0
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X"00000000", -- counter: .word 0
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others => X"00000000" );
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variable byte_address, word_address : natural;
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variable write_access : boolean;
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procedure do_write is
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subtype ls_2_bits is bit_vector(1 downto 0);
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begin
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case width is
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when dlx_mem_width_word =>
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mem(word_address) := to_bitvector(d);
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when dlx_mem_width_halfword =>
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if To_bit(a(1)) = '0' then -- ms half word
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mem(word_address)(0 to 15) := to_bitvector( d(0 to 15) );
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else -- ls half word
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mem(word_address)(16 to 31) := to_bitvector( d(16 to 31) );
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end if;
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when dlx_mem_width_byte =>
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case ls_2_bits'(To_bitvector(a(1 downto 0))) is
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when b"00" =>
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mem(word_address)(0 to 7) := to_bitvector( d(0 to 7) );
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when b"01" =>
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mem(word_address)(8 to 15) := to_bitvector( d(8 to 15) );
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when b"10" =>
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mem(word_address)(16 to 23) := to_bitvector( d(16 to 23) );
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when b"11" =>
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mem(word_address)(24 to 31) := to_bitvector( d(24 to 31) );
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end case;
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when others =>
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report "illegal width indicator in write" severity error;
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end case;
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end do_write;
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procedure do_read is
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begin
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d <= To_X01( mem(word_address) );
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end do_read;
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begin
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-- initialize outputs
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d <= disabled_dlx_word;
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ready <= '0';
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-- process memory cycles
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loop
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-- wait for a command, valid on leading edge of phi2
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wait on phi2 until rising_edge(phi2) and To_bit(mem_enable) = '1';
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-- decode address and perform command if selected
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byte_address := bv_to_natural(To_bitvector(a));
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write_access := To_bit(write_enable) = '1';
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if byte_address <= high_address then
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word_address := byte_address / 4;
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if write_access then -- write cycle
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do_write;
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wait for Tac_first; -- write access time, 1st cycle
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else -- read cycle
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wait for Tac_first; -- read access time, 1st cycle
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do_read;
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end if;
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-- ready synchronous with phi2
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wait until rising_edge(phi2);
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ready <= '1' after Tpd_clk_out;
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wait until falling_edge(phi2);
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ready <= '0' after Tpd_clk_out;
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-- do subsequent cycles in burst
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while To_bit(burst) = '1' loop
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word_address := (word_address + 1) mod (mem_size / 4);
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wait until rising_edge(phi2);
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if write_access then -- write cycle
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do_write;
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wait for Tac_burst; -- write access time, burst cycle
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else -- read cycle
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wait for Tac_burst; -- read access time, burst cycle
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do_read;
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end if;
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-- ready synchronous with phi2
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wait until rising_edge(phi2);
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ready <= '1' after Tpd_clk_out;
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wait until falling_edge(phi2);
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ready <= '0' after Tpd_clk_out;
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end loop;
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if not write_access then -- was read
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d <= disabled_dlx_word after Tpd_clk_out;
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end if;
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end if;
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end loop;
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end process mem_behavior;
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end architecture preloaded;
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