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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_fg_05_09.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- not in book
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entity computer_system is
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end entity computer_system;
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-- end not in book
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architecture abstract of computer_system is
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  subtype word is bit_vector(31 downto 0);
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  signal address : natural;
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  signal read_data, write_data : word;
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  signal mem_read, mem_write : bit := '0';
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  signal mem_ready : bit := '0';
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begin
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  cpu : process is
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                  variable instr_reg : word;
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                variable PC : natural;
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                -- . . .    -- other declarations
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  begin
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    loop
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      address <= PC;
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      mem_read <= '1';
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      wait until mem_ready = '1';
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      instr_reg := read_data;
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      mem_read <= '0';
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      wait until mem_ready = '0';
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      PC := PC + 4;
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      -- . . .    -- execute the instruction
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    end loop;
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  end process cpu;
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  memory : process is
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                     type memory_array is array (0 to 2**14 - 1) of word;
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                   variable store : memory_array := (
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                     -- . . .
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                     -- not in book
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                     0 => X"0000_0000",
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                     1 => X"0000_0004",
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                     2 => X"0000_0008",
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                     3 => X"0000_000C",
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                     4 => X"0000_0010",
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                     5 => X"0000_0014",
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                     others => X"0000_0000"
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				        -- end not in book
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                     );
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  begin
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    wait until mem_read = '1' or mem_write = '1';
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    if mem_read = '1' then
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      read_data <= store( address / 4 );
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      mem_ready <= '1';
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      wait until mem_read = '0';
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      mem_ready <= '0';
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    else
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      -- . . .    -- perform write access
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    end if;
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  end process memory;
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end architecture abstract;
(10-10/42)