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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_21_fg_21_03.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- code from book (in text)
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entity random_source is
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  generic ( min, max : natural;
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            seed : natural;
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            interval : delay_length );
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  port ( number : out natural );
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end entity random_source;
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-- end code from book
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architecture fudged of random_source is
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begin
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  process is
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            variable next_number : natural := seed;
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  begin
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    if next_number > max then
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      next_number := min;
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    end if;
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    number <= next_number;
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    next_number := next_number + 1;
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    wait for interval;
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  end process;
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end architecture fudged;
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entity test_bench is
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end entity test_bench;
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-- code from book
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architecture random_test of test_bench is
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  subtype bv11 is bit_vector(10 downto 0);
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  function natural_to_bv11 ( n : natural ) return bv11 is
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    variable result : bv11 := (others => '0');
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    variable remaining_digits : natural := n;
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  begin
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    for index in result'reverse_range loop
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      result(index) := bit'val(remaining_digits mod 2);
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      remaining_digits := remaining_digits / 2;
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      exit when remaining_digits = 0;
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    end loop;
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    return result;
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  end function natural_to_bv11;
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  signal stimulus_vector : bv11;
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  -- . . .
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begin
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  stimulus_generator : entity work.random_source
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    generic map ( min => 0, max => 2**10 - 1, seed => 0,
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                  interval => 100 ns )
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    port map ( natural_to_bv11(number) => stimulus_vector );
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  -- . . .
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end architecture random_test;
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-- end code from book
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