Project

General

Profile

Download (2.16 KB) Statistics
| Branch: | Tag: | Revision:
1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_20_fg_20_13.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
entity fg_20_13 is
28
end entity fg_20_13;
29

    
30

    
31
architecture test of fg_20_13 is
32

    
33
  attribute trace : string;
34

    
35
  subtype byte is bit_vector(7 downto 0);
36
  type byte_vector is array (natural range <>) of byte;
37

    
38
  type ram_bus is record
39
                    d : byte;
40
                    cmd, status, clk : bit;
41
                  end record ram_bus;
42

    
43
  -- code from book
44

    
45
  procedure mem_read ( address : in natural;
46
                       result : out byte_vector;
47
                       signal memory_bus : inout ram_bus ) is
48

    
49
    attribute trace of address : constant is "integer/hex";
50
    attribute trace of result : variable is "byte/multiple/hex";
51
    attribute trace of memory_bus : signal is
52
      "custom/command=rambus.cmd";
53
    -- . . .
54

    
55
  begin
56
    -- . . .
57
    -- not in book
58
    report address'trace;
59
    report result'trace;
60
    report memory_bus'trace;
61
    -- end not in book
62
  end procedure mem_read;
63

    
64
  -- end code from book
65

    
66
  signal memory_bus : ram_bus;
67

    
68
begin
69

    
70
  process is
71
            variable address : natural;
72
          variable result : byte_vector(0 to 3);
73
  begin
74
    mem_read ( address, result, memory_bus );
75
    wait;
76
  end process;
77

    
78
end architecture test;
(509-509/534)