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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_19_tb-jnsth.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library qsim;
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use std.textio.all;
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architecture join_synth of test_bench is
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  use qsim.qsim_types.all;
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  constant num_outputs : positive := 4;
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  signal fork_arc : arc_vector(1 to num_outputs);
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  signal join_arc : arc_type;
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  signal info_detail : info_detail_type := trace;
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begin
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  generator : process is
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  begin
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    fork_arc(1) <= (true,  ("generator           ", 9,  0, now));
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    fork_arc(2) <= (true,  ("generator           ", 9,  1, now));    wait for 0 ns;
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    fork_arc(3) <= (true,  ("generator           ", 9,  2, now));
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    fork_arc(4) <= (true,  ("generator           ", 9,  3, now));    wait for 10 ns;
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    fork_arc(1) <= (false, ("generator           ", 9,  4, now));
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    fork_arc(2) <= (false, ("generator           ", 9,  5, now));    wait for 0 ns;
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    fork_arc(3) <= (false, ("generator           ", 9,  6, now));
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    fork_arc(4) <= (false, ("generator           ", 9,  7, now));    wait for 0 ns;
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    fork_arc(1) <= (true,  ("generator           ", 9,  8, now));
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    fork_arc(2) <= (true,  ("generator           ", 9,  9, now));    wait for 0 ns;
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    fork_arc(3) <= (true,  ("generator           ", 9, 10, now));
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    fork_arc(4) <= (true,  ("generator           ", 9, 11, now));    wait for 0 ns;
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    fork_arc(1) <= (false, ("generator           ", 9, 12, now));
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    fork_arc(2) <= (false, ("generator           ", 9, 13, now));    wait for 0 ns;
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    fork_arc(3) <= (false, ("generator           ", 9, 14, now));
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    fork_arc(4) <= (false, ("generator           ", 9, 15, now));    wait for 10 ns;
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    wait;
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  end process generator;
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  join1 : entity qsim.join(behavior)
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    generic map ( name => "join1",
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                  time_unit => ns,
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                  info_file_name => "join1.dat" )
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    port map ( in_arc => fork_arc,
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               out_arc => join_arc,
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               info_detail => info_detail );
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  sink1 : entity qsim.sink(behavior)
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    generic map ( name => "sink1",
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                  time_unit => ns,
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                  info_file_name => "sink1.dat" )
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    port map ( in_arc => join_arc,
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               info_detail => info_detail );
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  forks : for index in 1 to num_outputs generate
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    constant index_string : string := integer'image(index);
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  begin
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    fork_monitor : process
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      variable L : line;
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    begin
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      wait on fork_arc(index);
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      write(L, string'("fork_monitor(" & index_string & "): at "));
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      write(L, now, unit => ns);
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      write(L, string'(", "));
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      write(L, fork_arc(index).token, ns);
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      writeline(output, L);
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    end process fork_monitor;
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  end generate forks;
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  sink_monitor : process
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    variable L : line;
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  begin
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    wait on join_arc;
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    write(L, string'("sink_monitor: at "));
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    write(L, now, unit => ns);
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    write(L, string'(", "));
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    write(L, join_arc.token, ns);
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    writeline(output, L);
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  end process sink_monitor;
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end architecture join_synth;
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