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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_15_regmpr-b.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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architecture behavior of reg_multiple_plus_one_out_reset is
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begin
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reg: process ( d, latch_en, out_en, reset )
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is
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variable latched_value : dlx_word;
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begin
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if To_bit(reset) = '1' then
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latched_value := X"0000_0000";
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elsif To_bit(latch_en) = '1' then
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latched_value := To_X01(d);
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end if;
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q0 <= latched_value after Tpd;
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for index in out_en'range loop
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if To_bit(out_en(index)) = '1' then
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q(index) <= latched_value after Tpd;
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else
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q(index) <= disabled_dlx_word after Tpd;
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end if;
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end loop;
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end process reg;
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end architecture behavior;
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