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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_15_alut.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package alu_types is
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  subtype alu_func is std_logic_vector(3 downto 0);
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  constant alu_add :     alu_func := "0000";
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  constant alu_addu :    alu_func := "0001";
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  constant alu_sub :     alu_func := "0010";
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  constant alu_subu :    alu_func := "0011";
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  constant alu_and :     alu_func := "0100";
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  constant alu_or :      alu_func := "0101";
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  constant alu_xor :     alu_func := "0110";
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  constant alu_sll :     alu_func := "1000";
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  constant alu_srl :     alu_func := "1001";
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  constant alu_sra :     alu_func := "1010";
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  constant alu_pass_s1 : alu_func := "1100";
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  constant alu_pass_s2 : alu_func := "1101";
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end package alu_types;
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