Project

General

Profile

Download (3.82 KB) Statistics
| Branch: | Tag: | Revision:
1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_14_fg_14_08.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
library ieee;  use ieee.std_logic_1164.all;
28

    
29
               entity buf is
30
                 port ( a : in std_logic;  y : out std_logic );
31
               end entity buf;
32

    
33

    
34
               architecture basic of buf is
35
               begin
36
                 y <= a;
37
               end architecture basic;
38

    
39

    
40

    
41

    
42
-- code from book
43

    
44
               library ieee;  use ieee.std_logic_1164.all;
45

    
46
               entity fanout_tree is
47
                 generic ( height : natural );
48
                 port ( input : in std_logic;
49
                        output : out std_logic_vector (0 to 2**height - 1) );
50
               end entity fanout_tree;
51

    
52
--------------------------------------------------
53

    
54
               architecture recursive of fanout_tree is
55

    
56
               begin
57

    
58
                 degenerate_tree : if height = 0 generate
59
                 begin
60
                   output(0) <= input;
61
                 end generate degenerate_tree;
62

    
63
                 compound_tree : if height > 0 generate
64
                   signal buffered_input_0, buffered_input_1 : std_logic;
65
                 begin
66

    
67
                   buf_0 : entity work.buf(basic)
68
                     port map ( a => input, y => buffered_input_0 );
69

    
70
                   subtree_0 : entity work.fanout_tree(recursive)
71
                     generic map ( height => height - 1 )
72
                     port map ( input => buffered_input_0,
73
                                output => output(0 to 2**(height - 1) - 1) );
74

    
75
                   buf_1 : entity work.buf(basic)
76
                     port map ( a => input, y => buffered_input_1 );
77

    
78
                   subtree_1 : entity work.fanout_tree(recursive)
79
                     generic map ( height => height - 1 )
80
                     port map ( input => buffered_input_1,
81
                                output => output(2**(height - 1) to 2**height - 1) );
82

    
83
                 end generate compound_tree;
84

    
85
               end architecture recursive;
86

    
87
-- end code from book
88

    
89

    
90

    
91
               library ieee;  use ieee.std_logic_1164.all;
92

    
93
               entity fg_14_08 is
94
               end entity fg_14_08;
95

    
96

    
97
               architecture test of fg_14_08 is
98

    
99
                 signal unbuffered_clock : std_logic;
100
                 signal buffered_clock_array : std_logic_vector(0 to 7);
101

    
102
               begin
103

    
104
                 -- code from book (in text)
105

    
106
                 clock_buffer_tree : entity work.fanout_tree(recursive)
107
                   generic map ( height => 3 )
108
                   port map ( input => unbuffered_clock,
109
                              output => buffered_clock_array );
110

    
111
                 -- end code from book
112

    
113
                 clock_gen : process is
114
                 begin
115
                   unbuffered_clock <= '1' after 5 ns, '0' after 10 ns;
116
                   wait for 10 ns;
117
                 end process clock_gen;
118

    
119
               end architecture test;
(403-403/534)