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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_14_fg_14_05.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               entity master_slave_flipflop is
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                 port ( phi1, phi2 : in std_logic;
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                        d : in std_logic;
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                        q : out std_logic );
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               end entity master_slave_flipflop;
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               architecture behavioral of master_slave_flipflop is
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                 signal master_d : std_logic;
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               begin
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                 master_d <= d when phi1 = '1';
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                 q <= master_d when phi2 = '1';
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               end architecture behavioral;
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-- code from book
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               library ieee;  use ieee.std_logic_1164.all;
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               entity shift_reg is
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                 port ( phi1, phi2 : in std_logic;
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                        serial_data_in : in std_logic;
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                        parallel_data : inout std_logic_vector );
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               end entity shift_reg;
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--------------------------------------------------
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               architecture cell_level of shift_reg is
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                 alias normalized_parallel_data :
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                   std_logic_vector(0 to parallel_data'length - 1)
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                   is parallel_data;
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                 component master_slave_flipflop is
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                                                   port ( phi1, phi2 : in std_logic;
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                                                          d : in std_logic;
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                                                          q : out std_logic );
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                 end component master_slave_flipflop;
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               begin
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                 reg_array : for index in normalized_parallel_data'range generate
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                 begin
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                   first_cell : if index = 0 generate
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                   begin
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                     cell : component master_slave_flipflop
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                       port map ( phi1, phi2,
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                                  d => serial_data_in,
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                                  q => normalized_parallel_data(index) );
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                   end generate first_cell;
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                   other_cell : if index /= 0 generate
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                   begin
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                     cell : component master_slave_flipflop
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                       port map ( phi1, phi2,
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                                  d => normalized_parallel_data(index - 1),
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                                  q => normalized_parallel_data(index) );
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                   end generate other_cell;
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                 end generate reg_array;
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               end architecture cell_level;
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-- end code from book
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               library ieee;  use ieee.std_logic_1164.all;
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               entity fg_14_05 is
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               end entity fg_14_05;
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               architecture test of fg_14_05 is
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                 signal phi1, phi2, serial_data_in : std_logic := '0';
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                 signal parallel_data : std_logic_vector(3 downto 0);
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               begin
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                 dut : entity work.shift_reg(cell_level)
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                   port map ( phi1 => phi1, phi2 => phi2,
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                              serial_data_in => serial_data_in,
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                              parallel_data => parallel_data );
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                 clock_gen : process is
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                 begin
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                   phi1 <= '1', '0' after 4 ns;
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                   phi2 <= '1' after 5 ns, '0' after 9 ns;
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                   wait for 10 ns;
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                 end process clock_gen;
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                 stimulus : process is
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                 begin
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                   serial_data_in <= '0';  wait until phi2 = '1';
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                   serial_data_in <= '1';  wait until phi2 = '1';
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                   serial_data_in <= '1';  wait until phi2 = '1';
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                   serial_data_in <= '0';  wait until phi2 = '1';
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                   serial_data_in <= '1';  wait until phi2 = '1';
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                   serial_data_in <= '1';  wait until phi2 = '1';
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                   serial_data_in <= '0';  wait until phi2 = '1';
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                   serial_data_in <= '1';  wait until phi2 = '1';
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                   serial_data_in <= '1';  wait until phi2 = '1';
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                   serial_data_in <= '0';  wait until phi2 = '1';
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                   serial_data_in <= '1';  wait until phi2 = '1';
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                   serial_data_in <= '1';  wait until phi2 = '1';
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                   serial_data_in <= '0';  wait until phi2 = '1';
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                   serial_data_in <= '1';  wait until phi2 = '1';
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                   serial_data_in <= '1';  wait until phi2 = '1';
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                   serial_data_in <= '0';
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                   wait;
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                 end process stimulus;
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               end architecture test;
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