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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_14_fg_14_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- not in book
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entity graphics_engine is
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end entity graphics_engine;
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-- end not in book
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architecture behavioral of graphics_engine is
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  type point is array (1 to 3) of real;
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  type transformation_matrix is array (1 to 3, 1 to 3) of real;
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  signal p, transformed_p : point;
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  signal a : transformation_matrix;
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  signal clock : bit;
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  -- . . .
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begin
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  transform_stage : for i in 1 to 3 generate
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  begin
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    cross_product_transform : process is
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                                        variable result1, result2, result3 : real := 0.0;
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    begin
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      wait until clock = '1';
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      transformed_p(i) <= result3;
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      result3 := result2;
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      result2 := result1;
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      result1 :=  a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
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    end process cross_product_transform;
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  end generate transform_stage;
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  -- . . .    -- other stages in the pipeline, etc
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  -- not in book
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  clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
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  stimulus : process is
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  begin
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    a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
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    p <= ( 10.0, 10.0, 10.0 );
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    wait until clock = '0';
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    p <= ( 20.0, 20.0, 20.0 );
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    wait until clock = '0';
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    p <= ( 30.0, 30.0, 30.0 );
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    wait until clock = '0';
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    p <= ( 40.0, 40.0, 40.0 );
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    wait until clock = '0';
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    p <= ( 50.0, 50.0, 50.0 );
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    wait until clock = '0';
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    p <= ( 60.0, 60.0, 60.0 );
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    wait;
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  end process stimulus;
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  -- end not in book
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end architecture behavioral;
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