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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_13_fg_13_17.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- not in book
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entity single_board_computer is
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end entity single_board_computer;
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-- end not in book
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architecture structural of single_board_computer is
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  -- . . .    -- type and signal declarations
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  -- not in book
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  subtype word is bit_vector(31 downto 0);
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  signal sys_clk : bit;
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  signal cpu_a_d, latched_addr : word;
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  -- end not in book
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  component processor is
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                        port ( clk : in bit;  a_d : inout word; -- . . . );
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                        -- not in book
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                        other_port : in bit := '0' );
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                      -- end not in book
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  end component processor;
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  component memory is
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                     port ( addr : in bit_vector(25 downto 0); -- . . . );
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                            -- not in book
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                            other_port : in bit := '0' );
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                   -- end not in book
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  end component memory;
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  component serial_interface is
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                               port ( clk : in bit;  address : in bit_vector(3 downto 0); -- . . . );
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                               -- not in book
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                               other_port : in bit := '0' );
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                             -- end not in book
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  end component serial_interface;
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begin
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  cpu : component processor
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    port map ( clk => sys_clk, a_d => cpu_a_d, -- . . . );
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               -- not in book
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               other_port => open );
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  -- end not in book
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  main_memory : component memory
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    port map ( addr => latched_addr(25 downto 0), -- . . . );
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               -- not in book
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               other_port => open );
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  -- end not in book
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  serial_interface_a : component serial_interface
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    port map ( clk => sys_clk, address => latched_addr(3 downto 0), -- . . . );
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               -- not in book
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               other_port => open );
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  -- end not in book
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  -- . . .
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end architecture structural;
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