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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_13_fg_13_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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-- not in book
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use work.serial_interface_defs.all;
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entity microcontroller is
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end entity microcontroller;
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-- end not in book
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36
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library ieee; use ieee.std_logic_1164.all;
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39
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architecture structure of microcontroller is
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use work.serial_interface_defs.serial_interface;
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-- . . . -- declarations of other components, signals, etc
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-- not in book
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signal buffered_phi1, buffered_phi2, serial_a_select : std_logic;
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signal internal_addr : std_logic_vector(1 downto 0);
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signal internal_data_bus : data_vector;
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signal serial_a_int_req, rx_data_a, tx_data_a : std_logic;
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-- end not in book
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begin
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serial_a : component serial_interface
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port map ( clock_phi1 => buffered_phi1,
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clock_phi2 => buffered_phi2,
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serial_select => serial_a_select,
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reg_address => internal_addr(1 downto 0),
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data => internal_data_bus,
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interrupt_request => serial_a_int_req,
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rx_serial_data => rx_data_a,
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tx_serial_data => tx_data_a );
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-- . . . -- other component instances
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end architecture structure;
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