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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_11_fg_11_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               package fg_11_12 is
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                 procedure init_synchronize ( signal synch : out std_logic );
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                 procedure begin_synchronize ( signal synch : inout std_logic;
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                                               Tdelay : in delay_length := 0 fs );
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                 procedure end_synchronize ( signal synch : inout std_logic;
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                                             Tdelay : in delay_length := 0 fs );
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               end package fg_11_12;
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               package body fg_11_12 is
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                 -- code from book
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                 procedure init_synchronize ( signal synch : out std_logic ) is
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                 begin
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                   synch <= '0';
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                 end procedure init_synchronize;
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                 procedure begin_synchronize ( signal synch : inout std_logic;
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                                               Tdelay : in delay_length := 0 fs ) is
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                 begin
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                   synch <= 'Z' after Tdelay;
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                   wait until synch = 'H';
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                 end procedure begin_synchronize;
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                 procedure end_synchronize ( signal synch : inout std_logic;
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                                             Tdelay : in delay_length := 0 fs ) is
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                 begin
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                   synch <= '0' after Tdelay;
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                   wait until synch = '0';
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                 end procedure end_synchronize;
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                 -- end code from book
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               end package body fg_11_12;
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