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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_11_fg_11_07.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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use work.MVL4.all;
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entity ROM is
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  port ( a : in MVL4_ulogic_vector(15 downto 0);
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         d : inout MVL4_logic_vector(7 downto 0);
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         rd : in MVL4_ulogic );
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end entity ROM;
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-- not in book
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architecture behavioral of ROM is
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begin
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end architecture behavioral;
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-- end not in book
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--------------------------------------------------
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use work.MVL4.all;
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entity SIMM is
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  port ( a : in MVL4_ulogic_vector(9 downto 0);
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         d : inout MVL4_logic_vector(31 downto 0);
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         ras, cas, we, cs : in MVL4_ulogic );
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end entity SIMM;
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-- not in book
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architecture behavioral of SIMM is
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begin
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end architecture behavioral;
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-- end not in book
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--------------------------------------------------
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-- not in book
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use work.MVL4.all;
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entity memory_subsystem is
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end entity memory_subsystem;
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-- end not in book
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architecture detailed of memory_subsystem is
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  signal internal_data : MVL4_logic_vector(31 downto 0);
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  -- . . .
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  -- not in book
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  signal internal_addr : MVL4_ulogic_vector(31 downto 0);
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  signal main_mem_addr : MVL4_ulogic_vector(9 downto 0);
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  signal ROM_select : MVL4_ulogic;
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  -- end not in book
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begin
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  boot_ROM : entity work.ROM(behavioral)
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    port map ( a => internal_addr(15 downto 0),
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               d => internal_data(7 downto 0),
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               rd => ROM_select );
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  main_mem : entity work.SIMM(behavioral)
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    port map ( a => main_mem_addr, d => internal_data, -- . . . );
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               -- not in book
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               ras => '0', cas => '0', we => '0', cs => '0' );
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  -- end not in book
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  -- . . .
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end architecture detailed;
(363-363/534)