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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_08_fg_08_05.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- not in book
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library ieee;  use ieee.std_logic_1164.all;
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               entity bus_sequencer is
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                 port ( rd, wr, sel, width, burst : out std_ulogic;
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                        addr_low_2 : out std_ulogic_vector(1 downto 0);
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                        ready : out std_ulogic;
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                        control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
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                        other_signal : out std_ulogic );
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               end entity bus_sequencer;
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----------------
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               library ieee;  use ieee.std_logic_1164.all;
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               entity state_register is
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                 port ( phi1, phi2 : in std_ulogic;
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                        next_state : in std_ulogic_vector(3 downto 0);
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                        current_state : out std_ulogic_vector(3 downto 0) );
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               end entity state_register;
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               architecture std_cell of state_register is
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               begin
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               end architecture std_cell;
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-- end not in book
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               architecture fsm of bus_sequencer is
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                 -- This architecture implements the sequencer as a finite state machine.
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                 -- NOTE: it uses the clock signals from clock_pkg to synchronize the fsm.
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                 signal next_state_vector : -- . . .;
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                   -- not in book
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                   std_ulogic_vector(3 downto 0);
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                 signal current_state_vector : std_ulogic_vector(3 downto 0);
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                 -- end not in book
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               begin
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                 bus_sequencer_state_register : entity work.state_register(std_cell)
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                   port map ( phi1 => work.clock_pkg.clock_phase1,
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                              phi2 => work.clock_pkg.clock_phase2,
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                              next_state => next_state_vector,
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                              -- . . . );
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                              -- not in book
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                              current_state => current_state_vector );
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                 -- end not in book
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                 -- . . .
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               end architecture fsm;
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