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 Copyright (C) 1996 Morgan Kaufmann Publishers, Inc

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 This file is part of VESTs (Vhdl tESTs).

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 VESTs is free software; you can redistribute it and/or modify it

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 under the terms of the GNU General Public License as published by the

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 Free Software Foundation; either version 2 of the License, or (at

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 your option) any later version.

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 VESTs is distributed in the hope that it will be useful, but WITHOUT

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 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License

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 for more details.

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 You should have received a copy of the GNU General Public License

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 along with VESTs; if not, write to the Free Software Foundation,

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 Inc., 59 Temple Place, Suite 330, Boston, MA 021111307 USA

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 $Id: ch_06_tofpb.vhd,v 1.2 20011026 16:29:34 paw Exp $

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 $Revision: 1.2 $

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architecture behavioral of to_fp is

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begin

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behavior : process (vec) is

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variable temp : bit_vector(vec'range);

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variable negative : boolean;

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variable int_result : integer;

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begin

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temp := to_bitvector(vec);

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negative := temp(temp'left) = '1';

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if negative then

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temp := not temp;

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end if;

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int_result := 0;

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for index in vec'range loop  sign bit of temp = '0'

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int_result := int_result * 2 + bit'pos(temp(index));

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end loop;

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if negative then

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int_result := (int_result)  1;

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end if;

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 convert to floating point and scale to [1, +1)

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r <= real(int_result) / real(2**15);

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end process behavior;

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end architecture behavioral;
