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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_06_srff-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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architecture behavioral of synch_sr_ff is
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begin
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behavior : process (clk) is
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constant Tpd_clk_out : time := 3 ns;
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begin
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if rising_edge(clk) then
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if To_X01(clr) = '1' then
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q <= '0' after Tpd_clk_out;
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elsif To_X01(set) = '1' then
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q <= '1' after Tpd_clk_out;
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end if;
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end if;
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end process behavior;
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end architecture behavioral;
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