|
1
|
|
|
2
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
|
|
3
|
|
|
4
|
-- This file is part of VESTs (Vhdl tESTs).
|
|
5
|
|
|
6
|
-- VESTs is free software; you can redistribute it and/or modify it
|
|
7
|
-- under the terms of the GNU General Public License as published by the
|
|
8
|
-- Free Software Foundation; either version 2 of the License, or (at
|
|
9
|
-- your option) any later version.
|
|
10
|
|
|
11
|
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
|
|
12
|
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
13
|
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
|
14
|
-- for more details.
|
|
15
|
|
|
16
|
-- You should have received a copy of the GNU General Public License
|
|
17
|
-- along with VESTs; if not, write to the Free Software Foundation,
|
|
18
|
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
19
|
|
|
20
|
-- ---------------------------------------------------------------------
|
|
21
|
--
|
|
22
|
-- $Id: ch_06_multt-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
|
|
23
|
-- $Revision: 1.2 $
|
|
24
|
--
|
|
25
|
-- ---------------------------------------------------------------------
|
|
26
|
|
|
27
|
library ieee; use ieee.std_logic_1164.all;
|
|
28
|
|
|
29
|
architecture bench of multiplier_test is
|
|
30
|
|
|
31
|
signal a, b : std_ulogic_vector(15 downto 0) := (others => '0');
|
|
32
|
signal p : std_ulogic_vector(31 downto 0);
|
|
33
|
|
|
34
|
begin
|
|
35
|
|
|
36
|
dut : entity work.multiplier(behavioral)
|
|
37
|
port map (a, b, p);
|
|
38
|
|
|
39
|
stimulus : process is
|
|
40
|
begin
|
|
41
|
a <= X"8000"; b <= X"8000"; -- -1 * -1
|
|
42
|
wait for 50 ns;
|
|
43
|
a <= X"0001"; b <= X"0001"; -- 2**-15 * 2**-15
|
|
44
|
wait for 50 ns;
|
|
45
|
a <= X"0001"; b <= X"0000"; -- 2**-15 * 0
|
|
46
|
wait for 50 ns;
|
|
47
|
a <= X"0000"; b <= X"0001"; -- 0 * 2**-15
|
|
48
|
wait for 50 ns;
|
|
49
|
a <= X"0001"; b <= X"8000"; -- 2**-15 * -1
|
|
50
|
wait for 50 ns;
|
|
51
|
a <= X"8000"; b <= X"0001"; -- -1 * 2**-15
|
|
52
|
wait for 50 ns;
|
|
53
|
a <= X"4000"; b <= X"4000"; -- 0.5 * 0.5
|
|
54
|
wait for 50 ns;
|
|
55
|
a <= X"C000"; b <= X"4000"; -- -0.5 * 0.5
|
|
56
|
wait for 50 ns;
|
|
57
|
a <= X"4000"; b <= X"C000"; -- 0.5 * -0.5
|
|
58
|
wait for 50 ns;
|
|
59
|
a <= X"C000"; b <= X"C000"; -- -0.5 * -0.5
|
|
60
|
wait for 50 ns;
|
|
61
|
wait;
|
|
62
|
end process stimulus;
|
|
63
|
|
|
64
|
end architecture bench;
|