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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_06_mult-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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architecture behavioral of multiplier is
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begin
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  behavior : process (a, b) is
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                              constant Tpd_in_out : time := 40 ns;
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                            variable negative_result  : boolean;
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                            variable op1 : std_ulogic_vector(15 downto 0);
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                            variable op2 : std_ulogic_vector(15 downto 0);
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                            variable result : std_ulogic_vector(31 downto 0);
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                            variable carry_in, carry : std_ulogic;
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  begin
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    op1 := to_X01(a);
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    op2 := to_X01(b);
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    -- make both operands positive, remembering sign of result
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    negative_result := (op1(15) = '1') xor (op2(15) = '1');
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    if (op1(15) = '1') then
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      carry := '1';
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      for index in 0 to 15 loop
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        carry_in := carry;
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        carry := carry_in and not op1(index);
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        op1(index) := not op1(index) xor carry_in;
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      end loop;
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    end if;
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    if (op2(15) = '1') then
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      carry := '1';
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      for index in 0 to 15 loop
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        carry_in := carry;
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        carry := carry_in and not op2(index);
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        op2(index) := not op2(index) xor carry_in;
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      end loop;
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    end if;
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    -- do long multiplication
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    result := (others => '0');
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    for count in 0 to 15 loop
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      carry := '0';
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      if (op2(count) = '1') then
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        for index in 0 to 15 loop
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          carry_in := carry;
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          carry := (result(index+count) and op1(index))
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                   or (carry_in and (result(index+count) xor op1(index)));
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          result(index+count) := result(index+count) xor op1(index) xor carry_in;
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        end loop;
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        result(count+16) := carry;
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      end if;
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    end loop;
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    -- result now contains unsigned product, with binary point
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    -- between bits 30 and 29.  assign output with sign adjusted.
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    if negative_result then
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      carry := '1';
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      for index in 0 to 31 loop
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        carry_in := carry;
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        carry := carry_in and not result(index);
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        result(index) := not result(index) xor carry_in;
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      end loop;
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    end if;
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    p <= result after Tpd_in_out;
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  end process behavior;
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end architecture behavioral;
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