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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_tb_05_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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entity add_1 is
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  port ( d0, d1, d2, d3 : in bit;
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         y0, y1, y2, y3 : out  bit );
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end entity add_1;
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architecture boolean_eqn of add_1 is
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begin
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  y0 <= not d0 after 4 ns;
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  y1 <= (not d1 and d0)
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        or (d1 and not d0) after 4 ns;
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  y2 <= (not d2 and d1 and d0)
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	or (d2 and not (d1 and d0)) after 4 ns;
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  y3 <= (not d3 and d2 and d1 and d0)
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	or (d3 and not (d2 and d1 and d0)) after 4 ns;
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end architecture boolean_eqn;
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entity buf4 is
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  port ( a0, a1, a2, a3 : in bit;
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         y0, y1, y2, y3 : out  bit );
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end entity buf4;
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architecture basic of buf4 is
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begin
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  y0 <= a0 after 2 ns;
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  y1 <= a1 after 2 ns;
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  y2 <= a2 after 2 ns;
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  y3 <= a3 after 2 ns;
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end architecture basic;
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package counter_types is
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  subtype digit is bit_vector(3 downto 0);
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end package counter_types;
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