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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_fg_05_27.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- not in book
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use work.counter_types.all;
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-- end not in book
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entity counter is
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  port ( clk, clr : in bit;
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         q0, q1 : out digit );
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end entity counter;
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--------------------------------------------------
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architecture registered of counter is
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  signal current_val0, current_val1, next_val0, next_val1 : digit;
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begin
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  val0_reg : entity work.reg4(struct)
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    port map ( d0 => next_val0(0), d1 => next_val0(1),
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               d2 => next_val0(2), d3 => next_val0(3),
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               q0 => current_val0(0), q1 => current_val0(1),
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               q2 => current_val0(2), q3 => current_val0(3),
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               clk => clk, clr => clr );
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  val1_reg : entity work.reg4(struct)
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    port map ( d0 => next_val1(0), d1 => next_val1(1),
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               d2 => next_val1(2), d3 => next_val1(3),
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               q0 => current_val1(0), q1 => current_val1(1),
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               q2 => current_val1(2), q3 => current_val1(3),
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               clk => clk, clr => clr );
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  incr0 : entity work.add_1(boolean_eqn) -- . . .;
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    -- not in book
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    port map ( d0 => current_val0(0), d1 => current_val0(1),
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               d2 => current_val0(2), d3 => current_val0(3),
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	       y0 => next_val0(0), y1 => next_val0(1),
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               y2 => next_val0(2), y3 => next_val0(3) );
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  -- end not in book
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  incr1 : entity work.add_1(boolean_eqn) -- . . .;
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    -- not in book
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    port map ( d0 => current_val1(0), d1 => current_val1(1),
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               d2 => current_val1(2), d3 => current_val1(3),
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	       y0 => next_val1(0), y1 => next_val1(1),
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               y2 => next_val1(2), y3 => next_val1(3) );
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  -- end not in book
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  buf0 : entity work.buf4(basic) -- . . .;
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    -- not in book
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    port map ( a0 => current_val0(0), a1 => current_val0(1),
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               a2 => current_val0(2), a3 => current_val0(3),
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	       y0 => q0(0), y1 => q0(1),
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               y2 => q0(2), y3 => q0(3) );
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  -- end not in book
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  buf1 : entity work.buf4(basic) -- . . .;
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    -- not in book
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    port map ( a0 => current_val1(0), a1 => current_val1(1),
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               a2 => current_val1(2), a3 => current_val1(3),
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	       y0 => q1(0), y1 => q1(1),
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               y2 => q1(2), y3 => q1(3) );
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  -- end not in book
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end architecture registered;
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