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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_fg_05_25.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity reg4 is
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  port ( clk, clr, d0, d1, d2, d3 : in bit;
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         q0, q1, q2, q3 : out bit );
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end entity reg4;
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architecture struct of reg4 is
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begin
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  bit0 : entity work.edge_triggered_Dff(behavioral)
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    port map (d0, clk, clr, q0);
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  bit1 : entity work.edge_triggered_Dff(behavioral)
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    port map (d1, clk, clr, q1);
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  bit2 : entity work.edge_triggered_Dff(behavioral)
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    port map (d2, clk, clr, q2);
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  bit3 : entity work.edge_triggered_Dff(behavioral)
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    port map (d3, clk, clr, q3);
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end architecture struct;
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