CristalCaveGem » LustreC » Lustrec-Tests

-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc

-- This file is part of VESTs (Vhdl tESTs).

-- VESTs is free software; you can redistribute it and/or modify it

-- under the terms of the GNU General Public License as published by the

-- Free Software Foundation; either version 2 of the License, or (at

-- your option) any later version. 

-- VESTs is distributed in the hope that it will be useful, but WITHOUT

-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

-- for more details. 

-- You should have received a copy of the GNU General Public License

-- along with VESTs; if not, write to the Free Software Foundation,

-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

-- ---------------------------------------------------------------------

--

-- $Id: ch_05_fg_05_25.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $

-- $Revision: 1.2 $

--

-- ---------------------------------------------------------------------

entity reg4 is

  port ( clk, clr, d0, d1, d2, d3 : in bit;

         q0, q1, q2, q3 : out bit );

end entity reg4;

architecture struct of reg4 is

begin

  bit0 : entity work.edge_triggered_Dff(behavioral)

    port map (d0, clk, clr, q0);

  bit1 : entity work.edge_triggered_Dff(behavioral)

    port map (d1, clk, clr, q1);

  bit2 : entity work.edge_triggered_Dff(behavioral)

    port map (d2, clk, clr, q2);

  bit3 : entity work.edge_triggered_Dff(behavioral)

    port map (d3, clk, clr, q3);

end architecture struct;