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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_ch_05_09.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_05_09 is
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end entity ch_05_09;
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----------------------------------------------------------------
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architecture test of ch_05_09 is
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  signal clk, reset, trigger, test0, test1 : bit := '0';
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begin
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  process_05_3_h : process is
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  begin
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    -- code from book:
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    wait until clk = '1';
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    -- end of code from book
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    report "clk rising edge detected";
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  end process process_05_3_h;
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  ----------------
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  process_05_3_i : process is
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  begin
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    -- code from book:
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    wait on clk until reset = '0';
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    -- end of code from book
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    report "synchronous reset detected";
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  end process process_05_3_i;
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  ----------------
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  process_05_3_j : process is
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  begin
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    -- code from book:
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    wait until trigger = '1' for 1 ms;
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    -- end of code from book
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    if trigger'event and trigger = '1' then
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      report "trigger rising edge detected";
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    else
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      report "trigger timeout";
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    end if;
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  end process process_05_3_j;
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  ----------------
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  -- code from book:
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  test_gen : process is
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  begin
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    test0 <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 40 ns;
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    test1 <= '0' after 10 ns, '1' after 30 ns;
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    wait;
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  end process test_gen;
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  -- end of code from book
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  ----------------
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  stimulus_05_3_h_i_j : process is
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  begin
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    clk <= '1' after 10 ns, '0' after 20 ns,
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           '1' after 30 ns, '0' after 40 ns,
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           '1' after 50 ns, '0' after 60 ns,
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           '1' after 70 ns, '0' after 80 ns;
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    reset <= '1' after 45 ns, '0' after 75 ns;
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    trigger <= '1' after 10 ns, '0' after 20 ns,
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               '1' after 30 ns, '0' after 40 ns;
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    wait;
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  end process stimulus_05_3_h_i_j;
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end architecture test;
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