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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_03_fg_03_02.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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-- test code:
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use work.test_bench_03_02.all;
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-- end test code
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library ieee;  use ieee.std_logic_1164.all;
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               entity mux4 is
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                 port ( sel : in sel_range;
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                        d0, d1, d2, d3 : in std_ulogic;
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                        z : out std_ulogic );
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               end entity mux4;
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               architecture demo of mux4 is
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               begin
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                 out_select : process (sel, d0, d1, d2, d3) is
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                 begin
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                   case sel is
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                     when 0 => 
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                       z <= d0;
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                     when 1 => 
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                       z <= d1;
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                     when 2 => 
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                       z <= d2;
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                     when 3 => 
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                       z <= d3;
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                   end case;
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                 end process out_select;
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               end architecture demo;
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