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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_03_ch_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity ch_03_03 is
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end entity ch_03_03;
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architecture test of ch_03_03 is
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begin
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  process_3_1_c : process is
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                            type mode_type is (immediate, other_mode);
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                          type opcode_type is (load, add, subtract, other_opcode);
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                          variable mode : mode_type;
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                          variable opcode : opcode_type;
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                          constant immed_operand : integer := 1;
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                          constant memory_operand : integer := 2;
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                          constant address_operand : integer := 3;
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                          variable operand : integer;
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                          procedure procedure_3_1_c is
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                          begin
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                            -- code from book:
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                            if mode = immediate then
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                              operand := immed_operand;
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                            elsif opcode = load or opcode = add or opcode = subtract then
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                              operand := memory_operand;
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                            else
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                              operand := address_operand;
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                            end if;
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                            -- end of code from book
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                          end procedure_3_1_c;
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  begin
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    mode := immediate;
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    procedure_3_1_c;
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    mode := other_mode;
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    opcode := load;
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    procedure_3_1_c;
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    opcode := add;
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    procedure_3_1_c;
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    opcode := subtract;
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    procedure_3_1_c;
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    opcode := other_opcode;
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    procedure_3_1_c;
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    wait;
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  end process process_3_1_c;
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end architecture test;
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