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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_03_ch_03_02.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_03_02 is
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end entity ch_03_02;
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architecture test of ch_03_02 is
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  signal sel : integer range 0 to 1 := 0;
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  signal input_0 : integer := 0;
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  signal input_1 : integer := 10;
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  signal result : integer;
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begin
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  process_3_1_b : process (sel, input_0, input_1) is
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  begin
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    -- code from book:
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    if sel = 0 then
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      result <= input_0;  -- executed if sel = 0
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    else
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      result <= input_1;  -- executed if sel /= 0
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    end if;
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    -- end of code from book
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  end process process_3_1_b;
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  stimulus : process is
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  begin
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    sel <= 1 after 40 ns;
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    input_0 <= 1 after 10 ns, 2 after 30 ns, 3 after 50 ns;
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    input_1 <= 11 after 15 ns, 12 after 35 ns, 13 after 55 ns;
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    wait;
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  end process stimulus;
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end architecture test;
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