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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_01_fg_01_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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architecture behav of reg4 is
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begin
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storage : process is
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variable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
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begin
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if en = '1' and clk = '1' then
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stored_d0 := d0;
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stored_d1 := d1;
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stored_d2 := d2;
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stored_d3 := d3;
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end if;
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q0 <= stored_d0 after 5 ns;
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q1 <= stored_d1 after 5 ns;
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q2 <= stored_d2 after 5 ns;
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q3 <= stored_d3 after 5 ns;
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wait on d0, d1, d2, d3, en, clk;
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end process storage;
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end architecture behav;
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