Project

General

Profile

Download (942 Bytes) Statistics
| Branch: | Tag: | Revision:
1
ERROR: Unable to parse source file : /home/adieumeg/Documents/Repositories/lustrec-tests/vhdl_json/vhdl_files/forth-cpu/vga.vhd
2
ERROR: Parse error at line 203 column 2:
3

    
4
193:  cs: entity work.clock_source_tb
5
194:   generic map(clock_frequency => clock_frequency, hold_rst => 2)
6
195:   port map(stop => stop, clk => clk, rst => rst);
7
196: 
8
197:  cs25MHz: entity work.clock_source_tb
9
198:   generic map(clock_frequency => 25000000, hold_rst => 2)
10
199:   port map(stop => stop, clk => clk25MHz, rst => rst25MHz);
11
200: 
12
201: 
13
202:  uut: work.vga_pkg.vt100
14
203:  port map(
15
      ^
16
204:   clk      => clk,
17
205:   clk25MHz => clk25MHz,
18
206:   rst      => rst,
19
207:   we       => we,
20
208:   char     => char,
21
209:   busy     => busy,
22
210:   o_vga    => physical);
23
211: 
24
212:  stimulus_process: process
25
213:  begin
26

    
27
WARN: Missing blame information for the following files:
28
WARN:   * vga.vhd
29
WARN: This may lead to missing/broken features in SonarQube
(20-20/21)