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ERROR: Unable to parse source file : /home/adieumeg/Documents/Repositories/lustrec-tests/vhdl_json/vhdl_files/forth-cpu/top.vhd
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ERROR: Parse error at line 168 column 13:
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158: -------------------------------------------------------------------------------
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159: -- The Main components
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160: -------------------------------------------------------------------------------
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161: 
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162: ------- Output assignments (Not in a process) ---------------------------------
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163: 
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164:  -- @warning These are both temporary measures for testing only!
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165:  -- rst        <= btnu_d;
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166:  cpu_wait   <= btnc_d;
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167: 
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168:  irq_block: block
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                 ^
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169:   signal rx_fifo_not_empty: std_ulogic := '0';
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170:   signal tx_fifo_not_empty: std_ulogic := '0';
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171: 
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172:   signal rx_fifo_not_empty_edge: std_ulogic := '0';
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173:   signal rx_fifo_full_edge:      std_ulogic := '0';
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174:   signal tx_fifo_not_empty_edge: std_ulogic := '0';
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175:   signal tx_fifo_full_edge:      std_ulogic := '0';
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176:   signal kbd_char_buf_new_edge:  std_ulogic := '0';
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177:  begin
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178:   rx_fifo_not_empty <= not rx_fifo_empty;
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WARN: Missing blame information for the following files:
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WARN:   * top.vhd
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WARN: This may lead to missing/broken features in SonarQube
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