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ERROR: Unable to parse source file : /home/adieumeg/Documents/Repositories/lustrec-tests/vhdl_json/vhdl_files/cnes_guidelines/rule/data/testcases/simple_registers.vhd
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ERROR: Parse error at line 33 column 7:
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23:    signal flipflop_3: std_logic;
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24:    signal flipflop_4: std_logic;
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25:    signal flipflop_5: std_logic;
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26: begin
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27:    -- (is_simple_register_of flipflop_0 i_a i_clock)
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28:    -- (not (is_async_register_of flipflop_0 i_a i_clock))
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29:    -- (not (is_sync_register_of flipflop_0 i_a i_clock))
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30:    process (i_clock)
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31:    begin
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32:       if (rising_edge(i_clock))
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33:       begin
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          ^
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34:          flipflop_0 <= i_a;
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35:       end if;
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36:    end process;
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37: 
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38:    -- (is_simple_register_of flipflop_1 i_a i_clock)
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39:    -- (not (is_async_register_of flipflop_1 i_a i_clock))
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40:    -- (not (is_sync_register_of flipflop_1 i_a i_clock))
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41:    process (i_clock)
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42:    begin
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43:       if (i_b = '1')
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WARN: Missing blame information for the following files:
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WARN:   * simple_registers.vhd
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WARN: This may lead to missing/broken features in SonarQube
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