CristalCaveGem » LustreC » Lustrec-Tests

library IEEE;

use IEEE.std_logic_1164.ALL;

entity latches is

   port

   (

      i_clock: in std_logic;

      i_reset: in std_logic;

      i_a:     in std_logic;

      i_b:     in std_logic;

      i_c:     in std_logic;

      o_a:     out std_logic;

      o_b:     out std_logic;

      o_c:     out std_logic

   );

end entity latches;

architecture Behavioral of latches is

   signal latch_0: std_logic;

begin

   -- Taken from Xilinx's documentation:

   -- "Latch With Positive Gate and Asynchronous Reset VHDL Coding Example"

   -- 'latch_0' undefined for ((i_reset = '0') and (i_b = '0')), requiring the

   -- use of memory (hence the latch).

   process (i_reset, i_a, i_b)

   begin

      if (i_reset = '1')

      then

         latch_0 <= '0';

      elsif (i_b = '1')

      then

         latch_0 <= i_a;

      end if;

   end process;

end architecture;