lustrec-tests/vhdl_json/vhdl_files/cnes_guidelines/rule/data/testcases/computational.vhd @ 78957d3d
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library IEEE; |
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use IEEE.std_logic_1164.ALL; |
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entity computational is |
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port
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(
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i_clock: in std_logic; |
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i_reset: in std_logic; |
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i_a: in std_logic; |
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i_b: in std_logic; |
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i_c: in std_logic; |
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o_a: out std_logic; |
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o_b: out std_logic; |
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o_c: out std_logic |
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);
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end entity computational; |
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architecture Behavioral of computational is |
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begin
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process (i_a, i_b, i_c) |
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begin
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o_a <= i_b; |
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if (i_a = '1') |
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then
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o_a <= i_c; |
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end if; |
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end process; |
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process (i_a, i_b, i_c) |
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begin
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if (i_a = '1') |
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then
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o_a <= i_c; |
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else
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o_a <= i_b; |
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end if; |
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end process; |
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process (i_c) |
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begin
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o_a <= i_a; |
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o_a <= i_b; |
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o_a <= i_c; |
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end process; |
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process (i_c) |
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begin
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if (i_a = '1') |
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then
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o_a <= i_c; |
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else
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o_a <= i_b; |
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end if; |
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o_a <= i_c; |
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end process; |
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end architecture; |