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ERROR: Unable to parse source file : /home/adieumeg/Documents/Repositories/lustrec-tests/vhdl_json/vhdl_files/cnes_guidelines/rule/data/include/registers_test.vhd
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ERROR: Parse error at line 28 column 7:
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18: 
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19: architecture Behavioral of registers_test is
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20:    signal flipflop_a: std_logic;
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21: begin
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22:    -- (is_simple_register_of flipflop_a i_a i_clock)
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23:    -- (not (is_async_register_of flipflop_a i_a i_clock))
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24:    -- (not (is_sync_register_of flipflop_a i_a i_clock))
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25:    process (i_clock)
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26:    begin
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27:       if (rising_edge(i_clock))
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28:       begin
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          ^
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29:          flipflop_a <= i_a;
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30:       end if;
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31:    end process;
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32: 
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33:    -- (is_simple_register_of flipflop_a i_a i_clock)
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34:    -- (not (is_async_register_of flipflop_a i_a i_clock))
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35:    -- (not (is_sync_register_of flipflop_a i_a i_clock))
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36:    process (i_clock)
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37:    begin
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38:       if (i_b = '1')
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WARN: Missing blame information for the following files:
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WARN:   * registers_test.vhd
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WARN: This may lead to missing/broken features in SonarQube
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