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library IEEE;
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use IEEE.std_logic_1164.all;
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entity centisecond_timer is
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generic
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(
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---- For implementation:
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-- g_clock_cycle_per_centisecond: natural := 500000
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---- For testing, we recommend using:
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g_clock_cycle_per_centisecond: natural := 8
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);
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port
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(
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i_clock: in std_logic; -- System clock.
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i_reset: in std_logic; -- System reset.
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i_raz: in std_logic; -- User triggered raz.
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i_enable: in std_logic; -- Time is passing.
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o_new_centisecond: out std_logic -- Centisecond pulse.
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);
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end centisecond_timer;
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architecture behavioral of centisecond_timer is
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-- Having a range of 0 to (CLOCK_CYCLE_PER_CENTISECOND - 1) seems less
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-- readable, so we start at 1.
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signal timer: natural range 1 to g_clock_cycle_per_centisecond;
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begin
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P_TIME_COUNTER: process (i_clock, i_reset)
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begin
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if (i_reset = '1')
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then
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timer <= 1;
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else
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if (rising_edge(i_clock))
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then
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if (i_raz = '1')
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then
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-- Reset has been requested.
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timer <= 1;
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else
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-- No reset has been requested.
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if
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(
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(i_enable = '0')
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or (timer >= g_clock_cycle_per_centisecond)
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)
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then
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timer <= 1;
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elsif (i_enable = '1')
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then
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timer <= (timer + 1);
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end if;
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end if;
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end if;
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end if;
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end process;
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o_new_centisecond <=
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i_enable
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when (timer >= g_clock_cycle_per_centisecond)
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else '0'
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;
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end;
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