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1 d93979b7 Arnaud Dieumegard
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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_03_fg_03_04.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity counter is
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  port ( clk, reset : in bit;  count : out natural );
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end entity counter;
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architecture behavior of counter is
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begin
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  incrementer : process is
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                          variable count_value : natural := 0;
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  begin
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    count <= count_value;
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    loop
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      loop
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        wait until clk = '1' or reset = '1';
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        exit when reset = '1';
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        count_value := (count_value + 1) mod 16;
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        count <= count_value;
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      end loop;
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      -- at this point, reset = '1'
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      count_value := 0;
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      count <= count_value;
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      wait until reset = '0';
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    end loop;
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  end process incrementer;
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end architecture behavior;