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library ieee;
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use ieee.std_logic_1164.all;
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entity two_counters_tb is
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end two_counters_tb;
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architecture behavior of two_counters_tb is
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  signal x,ok : boolean;
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  signal clk : std_logic := '0';
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begin
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  top_0: entity work.top(top_behav) port map (x,clk,ok);
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  clk <= '1' after 0.5 ns when clk = '0' else
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         '0' after 0.5 ns when clk = '1';
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  process (clk)
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  begin
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    x <= false;
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    assert false 
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      report "ok = " & boolean'image(ok) & " | clk = " & std_logic'image(clk)
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      severity note;
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  end process;
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end behavior;
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